1. Field of the Invention
Embodiments of the present invention relate to electrostatic chuck structures for a semiconductor manufacturing apparatus suitable for performing an etching process on a semiconductor wafer in an etching chamber.
2. Background of the Invention
Semiconductor devices are typically manufactured by forming a film on a semiconductor substrate and forming a specific pattern in the film to have an electrical characteristic.
The specific pattern may be formed by repeatedly performing a series of processes, such as chemical vapor deposition, sputtering, photolithography, etching, ion injection, and chemical and mechanical polishing. During the processes, a wafer chuck for supporting and fixing a semiconductor wafer may be used.
Semiconductor wafer processing technology that manufactures fine and large-capacity semiconductor devices may use single wafer processing and dry processing. Accordingly, where the semiconductor wafer has previously been fixed in place for processing by means of clamp or vacuum, an electrostatic chuck (ESC) is now widely used to fix the semiconductor wafer in place by an electrostatic force. The ESC may also supply a temperature regulating gas for uniformly maintaining the temperature of the semiconductor wafer.
FIG. 1, illustrates one example of a typical electrostatic chuck that fixes a semiconductor wafer by an electrostatic force. In this example, the electrostatic chuck is a ceramic type that includes an insulator and a conductor. The ceramic type electrostatic chuck may have a DC power supply for power application, a conductor to which DC power is applied, and an insulator surrounding the conductor. This electrostatic chuck supports the semiconductor wafer by an electrostatic force (e.g., Coulomb force). That is, power may be applied between the semiconductor wafer on the electrostatic chuck and a conductor electrode, such that positive and negative charges may be generated in the semiconductor wafer and the conductor electrode. Then, the semiconductor wafer is supported by the electrostatic force acting between the positive and negative charges.
However, in this type of electrostatic chuck implementation, in order to improve an etching rate of the semiconductor wafer on the electrostatic chuck and critical dimension (CD) uniformity, it is frequently necessary to adjust parameters, such as a kind of plasma source, processing conditions, and a gas distribution panel (GDP). The adjustment(s) may be complex, and such complexity causes an increase in an error rate in the manufacturing process, which deteriorates yield of the semiconductor device. There is thus a need for a new structure for an electrostatic chuck capable of improving the etching rate and the CD uniformity.